1. Field of the Invention
The present invention relates to control of word line activation in a semiconductor memory device.
2. Description of the Related Art
Commonly used semiconductor memory devices include DRAM and SRAM. It is common knowledge that while DRAM offers higher capacity at lower price than SRAM, it requires refresh operations. SRAM, on the other hand, while easier to use due to the lack of a need for refresh operations, is more expensive and has lower capacity than DRAM.
Virtual SRAM (known as VSRAM or PSRAM) is a semiconductor memory device that offers that advantages of both DRAM and SRAM. Virtual SRAM has a memory cell array composed of dynamic memory cells identical to those in DRAM, and also houses a refresh controller that allows refresh operations to be performed internally. Thus, external devices connected to virtual SRAM (such as a CPU) can access (i.e., read or write data) virtual SRAM without being aware of refresh operations. This feature of virtual SRAM is known as xe2x80x9crefresh transparency.xe2x80x9d
During each cycle in which virtual SRAM is accessed, the word line selected by an address must be activated and deactivated. However, in instances where, for example, the same word line is activated during consecutive cycles, repeated activation and deactivation of the word line during each cycle represents a waste of power. This problem is not limited to virtual SRAM, being common to all semiconductor memory devices in which word lines are repeatedly activated and deactivated in each cycle.
An object of the present invention is to provide a technique for reducing the power consumption associated with word line activation in semiconductor memory devices.
At least part of the above and the other related objects is attained by a semiconductor memory device. A semiconductor memory device includes: a plurality of memory cell blocks composed of dynamic memory cells arranged in a matrix, the memory cell block including a plurality of word lines; an address input section for input of a multiple-bit address that includes a block address for selecting any one block from among the plurality of memory cell blocks, and a row address for selecting one of the plurality of word lines in the selected memory cell block; a data input/output section for input/output of data corresponding to a memory cell selected by the multiple-bit address; and a word line activation controller for controlling activation of the word lines. The word line activation controller includes: a row address transition detector for detecting whether the row address has changed. (a) In a first case that the row address transition detector does not detect a change in the row address during consecutive cycles in which read or write operations of data for the memory cells are enabled and in which an identical row address is used, the word line activation controller can maintain an activated state of a word line activated in a first memory cell block during an initial cycle of the consecutive cycles, without deactivation thereof until a final cycle of the consecutive cycles. (b) In a second case that a refresh request is issued to perform a refresh operation on the first memory cell block while the activated word line in the first memory cell block is maintained in the activated state, the word line activation controller can deactivate the activated word line in the first memory cell block if no read or write operations of data are currently being performed in the first memory cell block. (c) In a third case that a read or write operation for the first memory cell block is requested within a predetermined period after the issuance of the refresh request to the first memory cell block, the word line activation controller can suspend the refresh operation for the first memory cell block, and activate the deactivated word line in the first memory cell block for the read or write operation of data.
The semiconductor memory device herein includes a word line activation controller. Where consecutive cycles use addresses that include the same given row address, the word line activation controller maintains a word line activated during the initial cycle in the activated state until the final cycle in which this same row address is used. In the event of a refresh request, the word line activation controller can deactivate the activated word line without waiting for the final cycle.
The word line activation controller herein can perform refresh operations in the semiconductor memory device, and also obviates the need to repeatedly activate and deactivate word lines in each cycle during periods in which no refresh operations are being performed, thereby reducing the power consumption associated with word line activation.
The advantages of the device herein are particularly notable in cases where data read/write operations on memory cells on an activated word line are performed in two or more cycles among a plurality of cycles that extend from an initial cycle to a final cycle.
When a data read or write operation is requested within a predetermined period after a request to perform a refresh operation, the refresh operation is suspended, and the word line for the data read or write operation is activated, whereby priority can be given to data read or write operations.
In the semiconductor memory device, it is preferable that the address input section is simultaneously supplied with a column address as well as with the row address; and the row address is assigned to a plurality of upper bits of the multiple-bit address.
By assigning the row address to a plurality of upper bits, the row address becomes relatively less likely to change, so that word lines can be more frequently maintained in the activated state, thereby reducing the power consumption associated with word line activation.
In the semiconductor memory device, it is also preferable that the predetermined period is substantially equal to a period required for precharging bit lines in the first memory cell block.
In this way precharging can be performed during the cycle period just prior to the cycle for which the data read or write operation has been requested, whereby individual cycle length can be made relatively short.
In the semiconductor memory device, it is preferable that the word line activation controller is capable of: in the first case, maintaining the activated state of the word line activated in the first memory cell block during the initial cycle, without deactivation thereof until the final cycle; and additionally, when a read or write operation of data on a memory cell in a second memory cell block different from the first memory cell block is performed during any arbitrary cycle among the consecutive cycles after the initial cycle, maintaining an activated state of a word line activated in the second memory cell block during the arbitrary cycle, without deactivation thereof until the final cycle. And it is preferable that the word line activation controller is capable of: in the second case, where a refresh request is issued for a refresh operation on the second memory cell block as well as on the first memory cell block, deactivating the activated word line in the second memory cell block if no read or write operations of data are currently being performed in the second memory cell block.
The arbitrary cycle among the consecutive cycles after the initial cycle may be a cycle other than the final cycle, or the final cycle.
With this word line activation controller, word lines can be held in the activated state in two or more memory cell blocks at the same time, thus enabling more frequent data read/write operations to memory cells on activated word lines during periods that no refresh operations are being performed. This reduces the power consumption associated with word line activation. When a refresh operation is requested, the activated word lines can be deactivated without waiting for the final cycle, and the refresh operation performed.
The present invention is also directed to a method for controlling activation of word lines in a semiconductor memory device. The semiconductor memory device includes: a plurality of memory cell blocks composed of dynamic memory cells arranged in a matrix, the memory cell block including a plurality of word lines; an address input section for input of a multiple-bit address that includes a block address for selecting any one block from among the plurality of memory cell blocks, and a row address for selecting one of the plurality of word lines in the selected memory cell block; and a data input/output section for input/output of data corresponding to a memory cell selected by the multiple-bit address. (a) In a first case that no change in the row address is detected during consecutive cycles in which read or write operations of data for the memory cells are enabled and in which an identical row address is used, an activated state of a word line activated in a first memory cell block during an initial cycle of the consecutive cycles is maintained without deactivation thereof until a final cycle of the consecutive cycles. (b) In a second case that a refresh request is issued to perform a refresh operation on the first memory cell block while the activated word line in the first memory cell block is maintained in the activated state, the activated word line in the first memory cell block is deactivated if no read or write operations of data are currently being performed in the first memory cell block. (c) In a third case that a read or write operation for the first memory cell block is requested within a predetermined period after the issuance of the refresh request to the first memory cell block, the refresh operation for the first memory cell block is suspended, and the deactivated word line in the first memory cell block for the read or write operation of data is activated.
The method herein affords advantages and effects similar to those derived from use of the device herein.
The invention may be embodied in any of a number of forms, for example, a semiconductor memory device; a word line activation control method therefor; a semiconductor memory system comprising a semiconductor memory device and a control device; a method for controlling a semiconductor memory device; or an electronic device comprising a semiconductor memory device.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with the accompanying drawings.